IRC Web Chat

irc.freenode.net #hackontest

News

September 26, 2008 - Congratulations to all the winners! More about the Hackontest event will follow...

Pre-Hacking dinner of OpenLieroX

Working inside the box

Bruce Peren's evaluation

Harald Welte's review

 
Forgot password

coreboot    

Created by Carl-Daniel Hailfinger, modified September 23, 2009 at 16:10:15 CET | This project has a total of 9 feature requests with 8 comments rated at 159 points | 12 unique implementers | Readiness: 9 features with at least three implementers rated at 159 points

coreboot (formerly known as LinuxBIOS) is a Free Software project aimed at replacing the proprietary BIOS/EFI (firmware) you can find in most of today's computers.

It performs just a little bit of hardware initialization (e.g. training DRAM) and then executes a so-called payload, for example a Linux kernel, NetBSD, DragonFlyBSD, FILO, GRUB2, OpenBIOS, Open Firmware, SmartFirmware, GNUFI (UEFI), Etherboot, ADLO (for booting Windows, FreeBSD and OpenBSD), Plan 9, or memtest86.

With coreboot, you can achieve boot times of 0.5 seconds from poweron to kernel and 5 seconds from poweron to working X11.

List of Implementers

35

Bring up the K8 (Athlon64) in coreboot v3    

The AMD K8 and successors are well-supported in coreboot version 2. The new coreboot v3 has a much cleaner design, cleaner code and better documentation. Port the current K8 code from v2 to v3 and clean it up.

This is the key requirement for supporting dozens of current desktop mainboards in v3 and will help validate the new design.

End user benefits: A new mainboard can be supported in a matter of hours with a few clicks instead of days/weeks of cutting and pasting code.

By the way, if we manage to implement this feature before Hackontest starts, we will work on porting the AMD 690G/SB600 (or the VIA K8T890 if the 690G/SB600 is already done) chipset support from v2 to v3.

The focus of the task, whichever it may be, is enabling the user to easily create support for a mainboard without having to look at or understand the code.

Feature promoted at 35 points
Feature created 2008-04-24 by Carl-Daniel Hailfinger
  Add comment.

2008-08-03 21:46 Carl-Daniel Hailfinger Since this feature depends on a few unimplemented bits of critical infrastructure, we have started to work on that infrastructure. Everything is coming along nicely and we expect to implement this feature within 24 hours of heavy collaboration during Hackontest.

30

Bring up coreboot v3 on an Asus eeepc     

The Asus eeepc is an ultraportable notebook computer with an estimated user base of ~1 million. Porting coreboot v3 would trigger interest in coreboot and provide a platform to stabilize new features on.

End user benefits: An eeepc user can remove the current xandros distro and install an alternative os (combined with gnewsense producing a full gnu system)

Feature promoted at 30 points
Feature created 2008-05-15 by wesmo
  Add comment.

2008-07-29 14:03 Carl-Daniel Hailfinger If this feature is selected, implementers will have to agree on a small subset of the requested feature.

2008-05-18 00:20 Stefan Reinauer Actually, porting would take more than 3 months just for the chipset alone, even if you have the full documentation.

2008-05-15 22:39 Carl-Daniel Hailfinger Sorry, this is not doable in 24 hours. Because key information about the chipset, processor and embedded controller is unavailable, we would need ~12 months of reverse engineering. Even if we had all the docs, porting would take a lot longer than 24 hours because of the embedded controller.

23

Create flashrom support for the EeePc    

The Asus EeePc is one of the best-selling subnotebooks right now, but it's not possible to reflash the ROM from a free operating system with free tools.

A first step towards firmware/BIOS modification or replacement is the ability to reflash the ROM. This is mostly a reverse engineering effort and will require intimate knowledge of SPI flash chips and SPI and LPC wire protocols. With a logic analyzer, it should be possible to watch the proprietary BIOS reflashing sequence, correlate SPI and LPC traffic and write up a specification for ROM reflashing.

The 24 hours of Hackontest will be used to gather SPI/LPC traffic traces, correlate them and implement the reverse engineered flashing protocol. Depending on the availability of hardware and tools, some of this task may need to be done in advance or completed after Hackontest.

There already is a version of flashrom that supports early prototypes of the OLPC XO which has a similar flash controller. That version will be used as a basis for the new development effort.

Feature promoted at 23 points
Feature created 2008-05-28 by Carl-Daniel Hailfinger
  Add comment.
16

Easy web interface to create coreboot ROMs    

Coreboot currently has a great build system, but you still have to download the sources, configure it with the right settings, compile it and prepare the ROM.

It would be great if coreboot had a web interface where you just select a mainboard model, click on the features you want, wait a few minutes and download a perfect coreboot ROM image for your board.

Offer a few stress-tested coreboot images for paranoid people who want to be sure the ROM image is safe.

Feature promoted at 16 points
Feature created 2008-06-25 by Carl-Daniel Hailfinger
  Add comment.
13

Add support for AMD Phenom processors    

Phenom processors are the latest and greatest stuff AMD has to offer. There is already preliminary support for older Phenom variants in coreboot, but newer Phenom models need slightly different code.

Port existing code to the latest Phenom variants and test it. Make sure the new Phenom code works on all supported socket AM2 boards.

Feature promoted at 13 points
Feature created 2008-07-03 by Carl-Daniel Hailfinger
  Add comment.
11

Offer a compat BIOS plugin    

Most operating systems still need 16bit code to boot.
Offer the option to integrate the LegacyBIOS compatibility layer into a streamlined coreboot build process so people can easily create coreboot images which are able to boot DOS/Windows.

The 16bit BIOS compatibility layer plugin will be strictly optional, the coreboot code itself stays pure 32bit code.

Feature promoted at 11 points
Feature created 2008-06-25 by Carl-Daniel Hailfinger
  Add comment.

2008-07-31 11:55 Carl-Daniel Hailfinger The compatibility BIOS plugin is now called SeaBIOS.

2008-07-03 20:36 wwx This will be nice for running old plain DOS software, which still exists today (industrial computers for example)

11

Add AMD 700 chipset series support to coreboot    

We want support for socket AM2+ mainboards. Most of these mainboards use AMD 700 chipsets, which are unsupported right now.

Add support for the AMD 790FX, 790X, 770, 780G, 740G, 780V, M780G chipsets and port coreboot to the most wanted boards with these chipsets.

Feature promoted at 11 points
Feature created 2008-07-03 by Carl-Daniel Hailfinger
  Add comment.

2009-09-23 16:10 Zheng Bao I have sent the code to my coworkers. It should be release in a while

10

Offer a compat EFI plugin    

Some newer operating systems can boot with EFI instead of BIOS. While EFI is an old legacy standard, there are people who absolutely want it.

Offer the option to integrate a UEFI/GNUFI compatibility layer into a streamlined coreboot build process so people can easily create coreboot images which are able to boot operating systems requiring EFI.

The EFI compatibility layer plugin will be strictly optional, the coreboot code itself stays pure 32bit legacy-free code.

Feature promoted at 10 points
Feature created 2008-06-25 by Carl-Daniel Hailfinger
  Add comment.
10

Add AMD 690 chipset series support to coreboot    

Socket AM2 mainboards with modern AMD chipsets are not supported in coreboot right now. That restricts coreboot to very few interesting current mainboards.

Add support for the AMD 690G, 690V, M690, M690V and M690T chipsets and port coreboot to the most wanted boards with these chipsets.

Feature promoted at 10 points
Feature created 2008-07-03 by Carl-Daniel Hailfinger
  Add comment.

2008-11-30 19:24 Carl-Daniel Hailfinger Support for the AMD 690/SB600 chipset has been added to coreboot a few weeks ago.